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SMARTsemi DDR4 Memory ICs

SMARTsemi DDR4 Memory ICs feature a power supply (JEDEC standard 1.2V) of VDD = 1.2V ± 5%, and VPP = 2.375V to 2.75V. The ICs have up to 8 banks (4 banks x 2 bank groups) for x 16 products. The DDR4 feature a Pseudo Open Drain (POD) interface with a Burst Length (BL) of 8 and 4 with Burst Chop (BC).

Features

  • Power supply (JEDEC standard 1.2V)
    • VDD = 1.2V ± 5%
    • VPP = 2.375V to 2.75V
  • 16 internal banks (x8)
    • 8 banks (4 banks x 2 bank groups) for x 16 product
  • Pseudo Open Drain (POD) interface
  • 8 and 4 with Burst Chop (BC) Burst Length (BL)
  • CAS Latency (CL)
    • 10,(11),12,(13),14,(15),16,(17),18,19,20,22,24
  • CAS Write Latency (CWL)
    • 9,10,11,12,14,16,18,20
  • On-Die Termination (ODT): nom. values of RZQ/7, RZQ/5 (RZQ = 240Ω)
  • Precharge auto precharge option for each burst access
  • Refresh: auto-refresh, self-refresh
  • Refresh cycles
  • Average refresh period
    • 7.8μs at 0°C ≤ TC ≤ +85°C or -40°C ≤ TC ≤ +85°C
    • 3.9μs at +85°C < TC ≤ +95°C
  • Double-data-rate architecture two data transfers per clock cycle
  • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
  • Bi-directional differential data strobe (DQS_t and DQS_c) is transmitted/received with data for capturing data at the receiver
  • Termination Data Strobe is supported (x8 only) (TDQS_t and TDQS_c)
  • DQS is edge-aligned with data for READs; center aligned with data for WRITEs
  • Differential clock inputs (CK_t and CK_c)
  • DLL aligns DQ and DQS transitions with CK transitions
  • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
  • Data Mask (DM) for writing data
  • Write Cyclic Redundancy Code (CRC) for DQ error detection and inform it to the controller during high-speed operation
  • Data Bus Inversion (DBI)
    • Improve the power consumption and signal integrity
    • of the memory interface (x16 product only)
  • Programmable preamble is supported by both of 1tCK and 2tCK mode
  • Command Address (CA) Parity for command/address signal error detect and inform it to a controller
  • VREFDQ training
    • VREFDQ generate inside DRAM and further trained per DRAM
  • Per DRAM Addressability (PDA)
    • Each DRAM can be set a different mode register value individually and has individual adjustments.
  • Fine granularity refresh
    • 2x, 4x mode for smaller tRFC
  • Programmable Partial Array Self-Refresh (PASR)
  • RESET_n pin for power-up sequence and reset function
  • Operating case temperature range:
    • Commercial: TC = 0°C to +95°C
    • Industrial: TC = -40°C to +95°C
View Results ( 7 ) Page
N.º de artículo Hoja de datos Descripción
KTDM8G4B832BGIBCT KTDM8G4B832BGIBCT Hoja de datos DRAM DDR4, 8Gb, 1Gbx8, 1600Mhz, 3200Mbps, 1.2V, 78-ball FBGA, Industrial temp
KTDM8G4B832BGCBCT KTDM8G4B832BGCBCT Hoja de datos DRAM DDR4, 8Gb, 1Gbx8, 1600Mhz, 3200Mbps, 1.2V, 78-ball FBGA, Commercial temp
KTDM4G4B626BGCEAT KTDM4G4B626BGCEAT Hoja de datos DRAM DRAM DDR4 4GB 256MX16 2666Mbps 1.2V 96-FBGA Commercial
KTDM4G4B826BGIEAT KTDM4G4B826BGIEAT Hoja de datos DRAM DRAM DDR4 4GB 512MX8 2666Mbps 1.2V 78-FBGA Industrial
KTDM4G4B826BGCEAT KTDM4G4B826BGCEAT Hoja de datos DRAM DRAM DDR4 4GB 512MX8 2666Mbps 1.2V 78-FBGA Commercial
KTDM8G4B632BGCBCT KTDM8G4B632BGCBCT Hoja de datos DRAM DDR4, 8Gb, 512Mbx16, 1600Mhz, 3200Mbps, 1.2V, 96-ball FBGA, Commercial temp
KTDM4G4B626BGIEAT KTDM4G4B626BGIEAT Hoja de datos DRAM DRAM DDR4 4GB 256MX16 2666Mbps 1.2V 96-FBGA Industrial
Publicado: 2022-10-17 | Actualizado: 2025-03-06