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Infineon Technologies FL-L NOR Flash Memory Family

Infineon Technologies FL-L NOR Flash Memory Family uses a 65nm process lithography and floating gate technology. The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). The FL-L family supports traditional SPI single-bit (Single I/O or SIO) and optional 2-bit (Dual I/O or DIO). Also, it supports four-bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands.

The FL-L family uses a Double Data Rate (DDR) read commands for QIO and QPI, which transfers address and reads data on both edges of the clock. The architecture presents a Page Programming Buffer that allows up to 256 Bytes to be programmed in one operation. The architecture also provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. The FL-L NOR Flash offers high densities, flexibility, and fast performance used by a variety of mobile or embedded applications.

Flash memory contributes an excellent storage solution for systems with limited space, signal connections, and power. In addition, Flash memory is ideal for code shadowing to RAM, executing code directly (XIP), and storing re-programmable data.

Features

  • Serial Peripheral Interface (SPI) with Multi-I/O
    • Clock polarity and phase modes 0 and 3
    • Double Data Rate (DDR) option
    • Quad peripheral Interface (QPI) option
    • Extended Addressing: 24- or 32-bit address options
    • Serial Command subset and footprint compatible with S25FL-A, S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI families
    • Multi I/O Command subset and footprint compatible with S25FL-P, S25FL-S and S25FS-S SPI families
  • Read
    • Commands: Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO, DDR Quad I/O
    • Modes: Burst Wrap, Continuous (XIP), QPI
    • Serial Flash Discoverable Parameters (SFDP) for configuration information
  • Program Architecture
    • 256 Bytes Page Programming buffer 3.0V FL-L Flash Memory
    • Program suspend and resume
  • Erase Architecture
    • Uniform 4KB Sector Erase
    • Uniform 32KB Half Block Erase
    • Uniform 64KB Block Erase
    • Chip erase
    • Erase suspend and resume
  • 100,000 Program-Erase Cycles
  • 20-year data retention, typical
  • 65nm Floating Gate Technology
  • Security features
    • Status and Configuration Register Protection
    • Four Security Regions of 256 Bytes each outside the main Flash array
    • Legacy Block Protection: Block range
    • Individual and Region Protection
      • Individual Block Lock: Volatile individual Sector/Block
      • Pointer Region: Non-Volatile Sector/Block range
      • Power Supply Lock-down, Password, or Permanent protection of Security Regions 2 and 3 and Pointer Region
  • Single Supply Voltage with CMOS I/O
    • 2.7V to 3.6V
  • Temperature Range
    • Industrial (–40°C to +85°C)
    • Industrial Plus (–40°C to +105°C)
    • Extended (–40°C to +125°C)
    • Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
    • Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
    • Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
  • Packages (all Pb-free)
    • 8-pin SOIC 208 mil (SOC008) — S25FL128L only
    • WSON 5 x 6mm (WND008) — S25FL128L only
    • WSON 6 x 8mm (WNG008) — S25FL256L only
    • 16-pin SOIC 300 mil (SO3016) — S25FL256L only
  • BGA-24 6 x 8mm
    • 5 x 5 ball (FAB024) footprint
    • 4 x 6 ball (FAC024) footprint

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Publicado: 2017-01-26 | Actualizado: 2024-04-11