Two SPI memory interfaces allow the EC to read its code from external SPI flash memory: private SPI and/or shared SPI. The Shared SPI interface allows for EC code to be stored in a shared SPI chip. The private SPI memory interface provides for a dedicated SPI flash that is only accessible by the EC.
Features
- ARM® Cortex®-M4 Processor Core
- Multi-purpose AES Cryptographic Engine
- Hardware support for ECB, CTR, CBC, and OFB AES modes
- Support for 128-bit, 192-bit, and 256-bit key length
- DMA interface to SRAM shared with the Hash engine
- 128KB SRAM (Code and Data)
- 96KB Optimized for Code
- 32KB Optimized for Data
- Cryptographic Hash Engine
- Support for SHA-1 and SHA-256
- DMA interface to SRAM shared with AES engine
Block Diagram
Technical Specs
Publicado: 2016-05-12
| Actualizado: 2022-03-11

